1. Field of the Invention
The present invention relates to a non-volatile memory and more particularly, a structure of a non-volatile memory cell and a structure of a non-volatile memory formed by a plurality of non-volatile memory cells in an array.
2. Description of the Prior Art
Non-volatile memories are commonly fabricated using a complementary metal oxide semiconductor (CMOS) process. Each of the non-volatile memory cells in a non-volatile memory is made such that it may perform a read operation, a program operation and an erase operation. A common problem with existing non-volatile memory cell structures is its endurance to multiple time programming/read/erase operation. The read device of the non-volatile memory cell is commonly placed in a diffusion region, and also functioned as an erase device or a program device. The electrical characteristics while reading a cell would therefore, besides the intentional threshold shifts, degrade due to the cumulated program or erase operations occurred in the shared active region. The number of cycles the non-volatile memory cell can endure without encountering an error is, therefore, not maximized.